Clock Gate Control Register 2 [CLKGATECTL2](Default Value: 0xXXXXXXXX)ΒΆ

Offset: 0x0004 Registername: CLKGATECTL2
Bit: R/W: Default/Hex Description
31:28 R/W 0x0 /
27:26 R/W 0x0
CLKGATECTL2_DCU0_L0L1_CLKG
  • 0x0:
  • 0x1:
  • 0x2:
25:24 R/W 0x0
CLKGATECTL2_DCU1_L0L1_CLKG
  • 0x0:
  • 0x1:
  • 0x2:
23:22 R/W 0x0
CLKGATECTL2_DCU_L2_CLKG
  • 0x0:
  • 0x1:
  • 0x2:
21:20 R/W 0x0 /
19:18 R/W 0x0
CLKGATECTL2_TEX1_CLKG
  • 0x0:
  • 0x1:
  • 0x2:
17:16 R/W 0x0
CLKGATECTL2_ITR1_CLKG
  • 0x0:
  • 0x1:
  • 0x2:
15:14 R/W 0x0
CLKGATECTL2_USE1_CLKG
  • 0x0:
  • 0x1:
  • 0x2:
13:12 R/W 0x0 /
11:10 R/W 0x0
CLKGATECTL2_TEX0_CLKG
  • 0x0:
  • 0x1:
  • 0x2:
9:8 R/W 0x0
CLKGATECTL2_ITR0_CLKG
  • 0x0:
  • 0x1:
  • 0x2:
7:6 R/W 0x0
CLKGATECTL2_USE0_CLKG
  • 0x0:
  • 0x1:
  • 0x2:
5:4 R/W 0x0
CLKGATECTL2_UCACHEL2_CLKG
  • 0x0:
  • 0x1:
  • 0x2:
3:2 R/W 0x0
CLKGATECTL2_TCU_L2_CLKG
  • 0x0:
  • 0x1:
  • 0x2:
1:0 R/W 0x0
CLKGATECTL2_PBE_CLKG
  • 0x0:
  • 0x1:
  • 0x2: