RegistersΒΆ
Offset: | Registername: REGISTER_NAME | ||
---|---|---|---|
Bit: | R/W: | Default/Hex | Description: |
31:0 | R/W | 0xFFFFFFFF | |
31:0 | R/W | 0x0 |
- Clock Gate Control Register [CLKGATECTL] (Default Value: 0xXXXXXXXX)
- Clock Gate Control Register 2 [CLKGATECTL2](Default Value: 0xXXXXXXXX)
- Clock Gate Status Register [CLKGATESTATUS](Default Value: 0xXXXXXXXX)
- Clock Gate -?- Register [CLKGATECTLOVR](Default Value: 0xXXXXXXXX)
- Power Register [POWER](Default Value: 0x00000000)
- Core ID Register [CORE_ID](Default Value: 0xXXXXXXXX)
- Core Revision Register [CORE_REVISION](Default Value: 0xXXXXXXXX)
- Core Revision Field 1 Register [CORE_REV_FIELD1](Default Value: 0xXXXXXXXX)
- Core Revision Field 2 Register [DESIGNER_REV_FIELD2](Default Value: 0xXXXXXXXX)
- Soft Reset Register [SOFT_RESET](Default Value: 0x00000000)