Clock Gate Control Register [CLKGATECTL] (Default Value: 0xXXXXXXXX)ΒΆ
Offset: 0x0000 | Registername: CLKGATECTL | ||
---|---|---|---|
Bit: | R/W: | Default/Hex | Description |
31:29 | / | 0x0 | / |
28 | R/W | 0x0 |
|
27:25 | / | 0x0 | / |
24 | R/W | 0x0 |
|
23:22 | / | 0x0 | / |
21:20 | R/W | 0x0 |
|
19:18 | R/W | 0x0 |
|
17:16 | R/W | 0x0 |
|
15:14 | R/W | 0x0 |
|
13:12 | R/W | 0x0 |
|
11:10 | R/W | 0x0 |
|
9:8 | R/W | 0x0 |
|
7:6 | R/W | 0x0 |
|
5:4 | R/W | 0x0 |
|
3:2 | R/W | 0x0 |
|
1:0 | R/W | 0x0 |
|