Clock Gate Status Register [CLKGATESTATUS](Default Value: 0xXXXXXXXX)ΒΆ
Offset: 0x0008 | Registername: CLKGATESTATUS | ||
---|---|---|---|
Bit: | R/W: | Default/Hex | Description |
31:25 | R/W | 0x0 | / |
24 | R/W | 0x0 | CLKGATESTATUS_BIF_CORE_CLKS |
23 | R/W | 0x0 | CLKGATESTATUS_DCU1_L0L1_CLKS |
22 | R/W | 0x0 | CLKGATESTATUS_DCU0_L0L1_CLKS |
21 | R/W | 0x0 | CLKGATESTATUS_DCU_L2_CLKS |
20 | R/W | 0x0 | CLKGATESTATUS_TA_CLKS |
19 | R/W | 0x0 | CLKGATESTATUS_IDXFIFO_CLKS |
18 | R/W | 0x0 | / |
17 | R/W | 0x0 | CLKGATESTATUS_TEX1_CLKS |
16 | R/W | 0x0 | CLKGATESTATUS_ITR1_CLKS |
15 | R/W | 0x0 | CLKGATESTATUS_USE1_CLKS |
14 | R/W | 0x0 | / |
13 | R/W | 0x0 | CLKGATESTATUS_TEX0_CLKS |
12 | R/W | 0x0 | CLKGATESTATUS_ITR0_CLKS |
11 | R/W | 0x0 | CLKGATESTATUS_USE0_CLKS |
10 | R/W | 0x0 | CLKGATESTATUS_UCACHEL2_CLKS |
9 | R/W | 0x0 | CLKGATESTATUS_TCU_L2_CLKS |
8 | R/W | 0x0 | CLKGATESTATUS_PBE_CLKS |
7 | R/W | 0x0 | CLKGATESTATUS_PDS_CLKS |
6 | R/W | 0x0 | CLKGATESTATUS_VDM_CLKS |
5 | R/W | 0x0 | CLKGATESTATUS_DPM_CLKS |
4 | R/W | 0x0 | CLKGATESTATUS_MTE_CLKS |
3 | R/W | 0x0 | CLKGATESTATUS_TE_CLKS |
2 | R/W | 0x0 | CLKGATESTATUS_TSP_CLKS |
1 | R/W | 0x0 | CLKGATESTATUS_ISP2_CLKS |
0 | R/W | 0x0 | CLKGATESTATUS_ISP_CLKS |